Digital Logic

EECC 341 Winter 2001

MY HOME PAGE RIT Computer Engineering


Visitors Since 3-Dec-2001


  

  Assignment #1, Due Thursday, December 20.

  Assignment #2, Due Thursday, January 10.

  Assignment #3, Due Thursday, January 17.

  Assignment #4, Due Friday, February 15.

  

For the following lecture notes you can download or view a lecture as an Acrobat PDF file, or as a Microsoft Powerpoint97 file:

12-4-2K1 Introduction to Digital Logic Design.
12-5-2K1 Number Systems and Conversion. Binary Addition/Subtraction. Negative Binary Number Representations.
12-6-2K1 Binary Multiplication/Division. Binary Codes.
12-11-2K1 Combinational Vs. Sequential Logic Circuits, Switching Algebra Axioms & Theorems.
12-13-2K1 Duality, Standard Combinational Logic Representations.
12-18-2K1 Combinational Circuit Analysis & Synthesis Examples, NAND-NAND, NOR-NOR Realizations.
12-20-2K1 Combinational Logic Minimization Using K-Maps.
1-9-2K2 Combinational Logic Hazards, Static Hazard Detection and Elimination using K-maps.
1-10-2K2 Combinational Logic Building Blocks: Encoders, Decoders, Three-state buffers, multiplexers, demultiplexers.
1-15-2K2 Implementing Logic Functions Using Multiplexers.
1-16-2K2 Combinational Arithmetic Circuits: Carry Ripple Adders, Carry Look-Ahead Adders, Subtractors, Combinational Array Multipliers.
1-22-2K2 Midterm Review.
1-23-2K2 Combinational Comparators & Shift Circuits.
1-29-2K2 Sequential Logic Circuits Memory Elements: Latches & Flip-Flops.
1-30-2K2 Synchronous State Machines, Characteristic Equations, State Machine Analysis.
2-5-2K2 State Machine Analysis: State Naming, Timing Diagrams, Additional Examples.
2-6-2K2 State Machine Design.
2-7-2K2 State Machine Design Using J-K Flip-Flops.
2-13-2K2 Registers & Counters.
2-14-2K2 Memory Devices: Read Only Memory (ROM), Random Access Memory (RAM).
2-20-2K2 Final Review.
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Tuesday, Wednesday, Thursday 5:00-5:50 PM Bldg. 9, Room 1149


  

Dr. Muhammad Shaaban
e-mail: meseec@osfmail.isc.rit.edu
Office: 17-2507 X2373


Office Hours:
My Winter 2001 schedule


  

Current: http://www.rit.edu/~meseec/eecc341-winter2001/


  

TThe course covers the specification, analysis and design of digital systems. This includes the study combinational and sequential systems using standard modules such as decoders, encoders, multiplexers, shifters, adders, registers and counters. The laboratory provides more insight into the physical and circuit aspects of the design and implementation of digital systems using SSI, MSI and LSI components as well as CAD tools.


  

Must be taken concurrently with 1016-265 ( Discrete Mathematics I).


  

Digital Design: Principles & Practices, Third Edition, John F. Wakerly, Prentice Hall, 2000.

Digital Systems Laboratory Manual, Lab. Kit.


  

Homework Assignments: 20%
Midterm: 25%
Laboratory: 30%
Final Exam: 25%


  

Attending all lecture sessions is expected.


  

1- Binary Logic Functions.
2- Number Systems and Conversion.
3- Binary Arithmetic.
4- Boolean Algebra: Axioms and Theorems, Duality, Standard Logic Representations.
5- Mixed logic.
6- Combinational Circuit Specification and Analysis.
7- NAND-NAND, NOR-NOR Logic Realizations.
8- Combinational logic minimization using K-maps.
9- Combinational Logic Building Blocks: Encoders, decoders, three state buffers, multiplexers, demultiplexers.
10- Realizing combinational logic functions using multiplexers.
11- Arithmetic Logic Circuits.
12- Sequential Logic Circuits: Latches, Flip-flops and clocking methods.
13- Design and Analysis of Synchronous Sequential State-Machines including counters.

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