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Final Exam: Thursday, February 21, 12:30-2:30PM
Building 9 Room 3139
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Visitors Since 23-Nov-2012
 
Project , Due 12:00 Noon Monday, February 18.
Assignment #1, Due Thursday, December 13.
Assignment #2, Due Thursday, December 20.
Assignment #3, Due Thursday, January 10.
Assignment #4, Due Tuesday, February 5.
Assignment #5, Do Not Submit.
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For the following lecture notes you can download or view a lecture as an Acrobat PDF file, or as a Microsoft Powerpoint97 file:
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11-27-2012
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Introduction to Computer Design, The Design Hierarchy, Technology Trends, Register Transfer Notation (RTN),
Instruction Set Architecture (ISA) Characteristics and Classifications, CISC Vs. RISC.
(Chapters 1, 2)
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11-29-2012
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MIPS RISC Instruction Set Architecture: Syntax, Addressing Modes, Instruction Formats, Encoding & Examples.
(Chapter 2)
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12-4-2012
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Central Processor Unit (CPU) & Computer System Performance Measures: CPI, CPU Execution Equation, Benchmarking, MIPS Rating,
Amdahl's Law.
(4th Edition: Chapter 1 - 3rd Edition: Chapter 4)
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12-11-2012
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CPU Design: MIPS Single Cycle Datapath, Control Unit Design.
(4th Edition: Chapter 4.1-4.4 - 3rd Edition: Chapter 5.1-5.4)
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12-18-2012
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CPU Design: MIPS Multicycle Datapath and Finite State Machine Control Unit Design.
(3rd Edition Chapter 5.5 - See handout - Not in 4th Edition)
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1-8-2013
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Microprogrammed CPU Control Design for MIPS. Exception Handling.
(3rd Edition - Microprogramming: 5.7,
Appendix C.
Exception Handling: Chapter 5.6 - See Handout - Not in 4th Edition )
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1-10-2013
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Effective CPI Reduction: CPU Instruction Pipelining, Pipeline Hazard Conditions, Data Forwarding. Compiler Instruction Scheduling.
Delayed Branch. Pipelined CPU Performance.
(4th Edition: Chapter 4.5-4.8 - 3rd Edition: Chapter 6.1-6.6)
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1-15-2013
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Midterm Review.
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1-22-2013
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Microprogramming Project.
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1-29-2013
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Removing The Ideal Main Memory Assumption. The Memory Hierarchy: Basic Cache Design & Performance.
(4th Edition: Chapter 5.1-5.3 - 3rd Edition: Chapter 7.1-7.3)
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2-7-2013
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The Memory Hierarchy: Main & Virtual Memory. (FYI)
(4th Edition: Chapter 5.2-5.4 - 3rd Edition: Chapter 7.3-7.4)
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2-12-2013
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Final Exam Review + Course Evaluation
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Tuesday, Thursday 4:00-5:50PM Building 9 (GLE) Room 3139
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 he course covers the important aspects of the design,
organization, and performance evaluation of modern computer systems. This includes: computer performance measures, instruction set architecture
classification, input/output organization, CPU datapath and control unit design, microprogramming, arithmetic and logic
unit design, and the memory hierarchy, including cache levels and virtual memory.
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Assembly Programming EECC250, Introduction to Digital Systems EECC341, Operating Systems (0603-440).
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Homework Assignments: 25%
Midterm: 25%
Microprogramming Project : 20%
Final Exam: 30%
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Attending all lecture sessions is expected.
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1- Introduction: Modern Computer Design Levels, Components, Technology Trends, Register Transfer Notation (RTN). [Chapters 1, 2]
2- Instruction Set Architecture (ISA) Characteristics and Classifications: CISC Vs. RISC. [Chapter 2]
3- MIPS: An Example RISC ISA. Syntax, Instruction Formats, Addressing Modes, Encoding & Examples. [Chapter 2]
4- Central Processor Unit (CPU) & Computer System Performance Measures. [Chapter 4]
5- CPU Organization: Datapath & Control Unit Design. [Chapter 5]
6- Microprogrammed Control Unit Design. [Chapter 5]
7- CPU Pipelining. [Chapter 6]
8- The Memory Hierarchy: Cache Design & Performance. [Chapter 7]
9- The Memory Hierarchy: Main & Virtual Memory. [Chapter 7]
10- Input/Output Organization & System Performance Evaluation. [Chapter 8]
11- Computer Arithmetic & ALU Design. [Chapter 3]
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